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fn7954 rev.4.00 page 1 of 23 mar 24, 2017 fn7954 rev.4.00 mar 24, 2017 ISL8130 advanced single universal pulse-width modulation (pwm) controll er datasheet the ISL8130 is a versatile controller that integrates control, output adjustment, monitoring, and protection functions into a single package for synchronous buck, standard boost, sepic, and flyback topologies. the ISL8130 provides simple, single feedback loop, voltage mode control with fast transien t response. the output voltage of the converter can be precisely regulated to as low as 0.6v. the switching frequency is adjustable from 100khz to 1.4mhz. the error amplifier features a 15mhz gain-bandwidth product and 6v/s slew rate that enable s fast transient response. the pwm duty cycle ranges from 0% to 100% in transient conditions. the capacitor from the enss pin to ground sets soft-start slew rate. the ISL8130 monitors the output voltage and generates a power-good (pgood) signal when soft-start sequence is complete and the output is within regulation. a built-in, overvoltage protection circuit pr events the output voltage from going above typically 115% of the set point. for a buck and buck-boost configuration, protection from overcurrent conditions is provided by monitoring the r ds(on) of the upper mosfet to inhibit the pwm operation appropriately. this approach improves efficiency by eliminating the need for a current sensing resistor. for other topologies, overcurrent protection is achieved using a current sensing resistor. features ? universal controller for multiple dc/dc converters ?wide input range - 4.5v to 5.5v - 5.5v to 28v ?programmable soft-start ? supports pre-biased load applications ? resistor-selectable switching frequency - 100khz to 1.4mhz ? external reference tracking mode ? fast transient response - high-bandwidth error amplifier ?extensive circuit pr otection functions - overvoltage, overcurrent, over-temperature ? pb-free (rohs compliant) applications ? power supplies for microprocessors/asics ? ethernet routers and switchers ? medical instrument power supplies related literature ? for a full list of related documents, visit our website - ISL8130 product page + - rt fb comp e nss ref osc vin 5.6v to 16v c 1 l 1 c 10 0.1f ugate ocset boot d 1 c 7 r 2 r 4 c 12 c 11 c 2 c 6 c 5 r 1 c 9 q 1 32v r 3 monitor and protection refin pgnd cdel phase pvcc sgnd vcc5 c 4 c 3 pgood r 5 c 8 isen r cs lgate refout c 14 c 15 r 6 47nf 174k 470pf 10k 12.1k 470pf 2.2f 220f x 2 10h 3.32k 0.1f 47.5k 499 5m figure 1. boost converter + -
ISL8130 fn7954 rev.4.00 page 2 of 23 mar 24, 2017 ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL8130iaz 8130 iaz -40 to +85 20 ld qsop m20.15 ISL8130irz 81 30irz -40 to +85 20 ld 4x4 qfn l20.4x4 notes: 1. add ?-tk? suffix for 1k unit or ?-t7a? suffix for 250 unit tape and reel options. refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL8130 for more information on msl, see techbrief tb363 . pin configurations ISL8130 (20 ld qfn) top view ISL8130 (20 ld qsop) top view pin descriptions pin # qfn, qsop symbol i/o description 1, 8 isen i input to overcurrent protection comparator. voltag e on this pin is compared with voltage on ocset pin to detect an overcurrent condition. connect this pin to the junction of the inductor and a current sensing resistor in a boost, sepic, and flyback config uration. connect this pin to the phase node for sensing the voltage drop across the upper mosfet in a buck configuration. see ? overcurrent protection ? on page 14 for details. 2, 9 refin i to use refin as input reference, connect the desire d reference voltage to the refin pin in the range of 0.6v to 1.25v. to use internal reference voltage, tie this pin to vcc5. do not leave the refin pin floating. 3, 10 ocset i an internal current source draws 100a throug h a resistor connected between the supply and this pin. voltage at this pin is compared with voltage at th e isen pin for detecting an overcurrent condition. 4, 11 refout o this pin provides buffered reference output fo r refin. connect 2.2f decoupling capacitor to this pin. 5, 12 nc no connect 6, 13 vcc5 this pin is the output of the internal 5v ldo. connect a minimum of 4.7f ceramic decoupling capacitor as close to the ic as possible at this pin. refer to table 1 on page 14 . 7, 14 vin this pin powers the controller and must be decoupled to ground using a ceramic capacitor as close as possible to the vin pin. isen refin ocset nc boot ugate phase pvcc lgate vin sgnd rt fb refout vcc5 1 2 3 4 5 678910 15 14 13 12 11 20 19 18 17 16 pgnd cdel pgood enss comp 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 cdel pgnd lgate pvcc phase ugate isen boot refin ocset pgood comp fb rt enss sgnd vin vcc5 nc refout ep
ISL8130 fn7954 rev.4.00 page 3 of 23 mar 24, 2017 8, 15 sgnd this pin provides the signal ground for the ic. ti e this pin to the ground plane through the lowest impedance connection. 9, 16 rt i this is the oscillator frequency selection pin. connecting this pin directly to vcc5 will select the oscillator free running frequency of 300khz. by placing a resistor from this pin to gnd, the oscillator frequency can be programmed from 100khz to 1.4mhz. figure 2 shows the oscillator frequency vs rt resistance. 10, 17 fb i this pin is connected to the feedback resistor divider and provides the voltage feedback signal for the controller. this pin sets the output voltage of the converter. 11, 18 comp i/o this pin is the error amplifier output pin. it is used as the compensation point for the pwm error amplifier. 12, 19 enss i this pin provides enable/disable function and soft-start for the pwm output. the output drivers are turned off when this pin is held below 1v. 13, 20 pgood o this pin provides a power-good status. it is an open collector output used to indicate the status of the output voltage. 14, 1 cdel i the pgood signal can be delayed by a time prop ortional to a cdel current of 2a and the value of the capacitor connected between this pin and ground . a 0.1f will typically provide 125ms delay. 15, 2 pgnd this pin provides the power ground for the ic. tie this pin to the ground plane through the lowest impedance connection. 16, 3 lgate o this pin provides the pwm-controlled gate drive for the lower mosfet in buck and buck-boost configuration. 17, 4 pvcc this pin is the power connection for the gate driv ers. connect this pin to the vcc5 pin. connect a minimum of 1.0f ceramic decoupling capacitor as close to the ic as possible at this pin. 18, 5 phase this pin also provides a return path for the upper gate driver. in a buck configuration, it is the junction point of the inductor, the upper mosfet source, and the lower mosfet drain. for boost, sepic, and flyback configurations, this pin is tied to the power ground. 19, 6 ugate o this pin provides the pwm-controlled gate driv e for the main switching mosf et in all configurations. 20, 7 boot this pin is used to generate level-shifted gate drive signals on the ugate pin. connect this pin to the junction of the bootstrap capacitor and the cathode of the bootst rap diode in a buck or buck-boost configuration. for other topologies, connect this pin to pvcc. please refer to typical application circuits beginning on page 5 for details. 21 (qsop only) ep this pad is electrically isolated. connect this pad to the signal ground plane using at least five vias for a robust thermal conduction path. pin descriptions (continued) pin # qfn, qsop symbol i/o description 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 0 25 50 75 100 125 150 rt (k) frequency (khz) figure 2. oscillator frequency vs rt
fn7954 rev.4.00 page 4 of 23 mar 24, 2017 ISL8130 block diagram figure 3. block diagram boot ugate ep (qfn only) phase enss refout fb comp refin pgnd lgate ea pwm pvcc vcc5 gate control logic rt isen cdel pgood pgood comp vin linear ocset 100a ov/uv comp oscillator comp internal sgnd power-on reset (por) 10a ssdone ssdone enss ssdone fault logic otp ss v ref 0.6v voltage control overcurrent comp regulator
ISL8130 fn7954 rev.4.00 page 5 of 23 mar 24, 2017 typical step down dc/dc application schematic figure 4. typical step down dc/dc application schematic + - rt fb comp enss ref + - osc vin 5.5v to 27v c 1 l 1 c 10 0.1f ugate ocset phase boot d 1 q 1 c 7 r 2 r 4 c 12 c 11 c 2 c 6 c 5 r 1 c 9 lgate q 2 v out r 3 monitor and protection + - refin refout cdel pgnd pvcc sgnd vcc5 c 4 c 3 pgood r 5 c 8 isen typical standard boost dc/dc application schematic figure 5. typical standard boost dc/dc application schematic + - rt fb comp e nss ref + - osc vin 5.6v to 16v c 1 l 1 c 10 0.1f ugate ocset boot d 1 c 7 r 2 r 4 c 12 c 11 c 2 c 6 c 5 r 1 c 9 q 1 32v r 3 monitor and protection + - refin pgnd cdel phase pvcc sgnd vcc5 c 4 c 3 pgood r 5 c 8 isen r cs lgate refout c 14
ISL8130 fn7954 rev.4.00 page 6 of 23 mar 24, 2017 typical sepic dc/dc application schematic figure 6. typical sepic dc/dc application schematic + - rt fb comp e nss ref + - osc vin 8.4v to 19v c 1 l 1 c 10 0.1f ugate ocset boot d 1 c 7 r 2 r 4 c 12 c 11 c 2 c 6 c 5 r 1 c 9 q 1 12v r 3 monitor and protection + - refin pgnd cdel phase pvcc sgnd vcc5 c 4 c 3 pgood r 5 c 8 isen r cs lgate coupled inductor c 13 refout c 14
ISL8130 fn7954 rev.4.00 page 7 of 23 mar 24, 2017 absolute maximum rating s thermal information vin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +30v phase, boot, and u gate pins to gnd . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc +0.3v pvcc, vcc5, pgood, refin, and cdel to gnd . . . . . . . . . . . . . . . -0.3v to +6v lgate, enss, comp, fb and rt to gnd . . . . . . . . . . . . . . .-0.3v to vcc5 + 0.3v ocset and isen to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +27v ocset to isen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7v to +27v esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . 150v charged device model (tested per jesd22-c101e). . . . . . . . . . . . 1.5kv latch-up (tested per jesd-78c; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) qfn package ( notes 4 , 6 ) . . . . . . . . . . . . . . 43 6.5 qsop package ( notes 5 , 7 ). . . . . . . . . . . . . 90 52 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c ambient temperature range . . . . . . . . . . . . -40c to +85c (for ?i? suffix) junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions vin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to +24v ocset to vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.4v to +0.3v ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high-effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 6. for ? jc , the "case temp" location is the center of the exposed metal pad on the package underside. 7. for ? jc , the ?case temp? location is taken at the package top center. electrical specifications operating conditions: v in = 12v, pvcc shorted with vcc5, t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. parameter symbol test conditions min ( note 13 )typ max ( note 13 )unit v in supply current shutdown current ( note 8 )i vin_shdn en/ss = gnd - 1.4 - ma operating current ( notes 8 , 9 )i vin_op - 2.0 3.0 ma vcc5 supply ( notes 9 , 10 ) input voltage range v in = vcc5 for 5v configuration 4.5 5.0 5.5 v output voltage v in = 5.6v to 28v, i l = 3ma to 50ma 4.5 5.0 5.5 v maximum output current v in = 12v 50 - - ma power-on reset rising vcc5 threshold v in connected to vcc5, 5v input operation 4.310 4.400 4.475 v falling vcc5 threshold 4.090 4.100 4.250 v uvlo threshold hysteresis 0.16 - - v pwm converters maximum duty cycle f sw = 300khz 90 96 - % minimum duty cycle f sw = 300khz - - 0 % fb pin bias current -80- na undervoltage protection v uv fraction of the set point; ~3s noise filter 75 - 85 % overvoltage protection v ovp fraction of the set point; ~1s noise filter 112 - 120 % oscillator free running frequency r t = vcc5, t a = -40c to +85c 270 300 330 khz total variation t a = -40c to +85c, with frequency set by external resistor at r t -10%- % frequency range (set by rt) v in = 12v 100 - 1400 khz
ISL8130 fn7954 rev.4.00 page 8 of 23 mar 24, 2017 ramp amplitude ( note 11 ) ? v osc -1.25- v p-p reference and soft-start/enable internal reference voltage v ref 0.594 - 0.606 v soft-start current i ss -10- a soft-start threshold v soft 1.0 - - v enable low (converter disabled) --1.0v pwm controller gate drivers gate drive pull-down resistance -2.0- gate drive pull-up resistance -2.6- rise time co = 3300pf - 25 - ns fall time co = 3300pf - 25 - ns dead time between drivers -20- ns error amplifier dc gain ( note 11 ) -88- db gain-bandwidth product ( note 11 ) gbw - 15 - mhz slew rate ( note 11 )sr -6-v/s comp source/sink current ( note 11 ) 0.4 ma overcurrent protection ocset current source i ocset v ocset = 4.5v 80 100 120 a power-good and control functions power-good lower threshold v pg- fraction of the set point; ~3s noise filter -14 -10 -8 % power-good higher threshold v pg+ fraction of the set point; ~3s noise filter 9 - 16 % pgood leakage current i pglkg v pullup = 5.0v ( note 12 )--1a pgood voltage low i pgood = 4ma - - 0.5 v pgood delay cdel = 0.1f - 125 - ms cdel current for pgood cdel threshold = 2.5v - 2 - a cdel threshold -2.5- v external reference min external reference input at refin - 0.600 - v max external reference input at refin - - 1.250 v reference buffer buffered output voltage - internal reference v refout i refout = 1ma, c refout = 2.2f, t a = -40c to +85c 0.583 0.595 0.607 v buffered output voltage - internal reference v refout i refout = 20ma, c refout = 2.2f, t a = -40c to +85c 0.575 0.587 0.599 v buffered output voltage - external reference v refout v refin = 1.25v, i refout = 1ma, c refout = 2.2f, t a = -40c to +85c 1.227 1.246 1.265 v electrical specifications operating conditions: v in = 12v, pvcc shorted with vcc5, t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 13 )typ max ( note 13 )unit
ISL8130 fn7954 rev.4.00 page 9 of 23 mar 24, 2017 buffered output voltage - external reference v refout v refin = 1.25v, i refout = 20ma, c refout = 2.2f, t a = -40c to +85c 1.219 1.238 1.257 v current drive capability c refout = 2.2f 20 - - ma thermal shutdown shutdown temperature ( note 11 ) - 150 - c thermal shutdown hysteresis ( note 11 ) -20- c notes: 8. the operating supply current and shutdown current specifications for 5v input are the same as v in supply current specifications, i.e., 5.6v to 28v input conditions. these should also be tested with part configured for 5v input configuration, i.e., v in = vcc5 = pvcc = 5v. 9. this is the v cc current consumed when the device is active but not switching. does not include gate drive current. 10. when the input voltage is 5.6v to 28v at the vin pin, the vcc5 pin provides a 5v output capable of 50ma (max) total from the internal ldo. when the input voltage is 5v, the vcc5 pin will be used as a 5v inpu t, the internal ldo regulator is disabled and the vin must be co nnected to the vcc5. in both cases the pvcc pin should always be connected to the vcc5 pin (refer to ? functional description ? on page 14 for more details). 11. limits established by characteriza tion and are not production tested. 12. it is recommended to use vcc5 as the pull-up source. 13. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established b y characterization and are not production tested. electrical specifications operating conditions: v in = 12v, pvcc shorted with vcc5, t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 13 )typ max ( note 13 )unit typical performance curves oscilloscope plots are taken using the ISL8130eva l1z evaluation board for buck converter or ISL8130eval2z for boost converter, v in = 12v, v out = 5v for buck converter or v out = 32v for boost converter unless otherwise noted. figure 7. shutdown current, i vin_shdn vs temperature figure 8. shutdown current, i vin_shdn vs v in temperature (c) i vin_shdn (ma) -40 -15 10 35 60 85 1.00 1.25 1.50 1.75 2.00 v in (v) i vin_shdn (ma) 1.00 1.25 1.50 1.75 2.00 4 8 12 16 20 24 28
ISL8130 fn7954 rev.4.00 page 10 of 23 mar 24, 2017 figure 9. operating current i vin_op vs temperature figure 10. operating current i vin_op vs v in figure 11. v vcc vs temperature figure 12. v vcc vs i vcc figure 13. v ref vs temperature figure 14. f sw vs temperature typical performance curves oscilloscope plots are taken using the ISL8130eva l1z evaluation board for buck converter or ISL8130eval2z for boost converter, v in = 12v, v out = 5v for buck converter or v out = 32v for boost converter unless otherwise noted. (continued) i vin_op (ma) -40 -15 10 35 60 85 1.00 1.50 2.00 2.50 3.00 temperature (c) i vin_op (ma) 4 8 12 16 20 24 28 0 1 2 3 4 v in (v) v vcc (v) -40 -15 10 35 60 85 4.90 4.95 5.00 5.05 5.10 temperature (c) i vcc (a) v vcc (v) 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 0 0.010.020.030.040.05 v ref (v) -40 -15 10 35 60 85 0.590 0.595 0.600 0.605 0.610 temperature (c) f sw (khz) 270 280 290 300 310 320 -40 -15 10 35 60 85 temperature (c)
ISL8130 fn7954 rev.4.00 page 11 of 23 mar 24, 2017 figure 15. i ocset vs temperature figure 16. soft-start current, i ss vs temperature figure 17. v fb vs v refin figure 18. cdel current for pgood, i cdel vs temperature figure 19. soft-start waveform, no pre-biased, buck converter figure 20. soft-start waveform, pre-biased, buck converter typical performance curves oscilloscope plots are taken using the ISL8130eva l1z evaluation board for buck converter or ISL8130eval2z for boost converter, v in = 12v, v out = 5v for buck converter or v out = 32v for boost converter unless otherwise noted. (continued) i ocset normalized 0.85 0.95 1.05 1.15 -40 -15 10 35 60 85 temperature (c) i ss ( a) 8 9 10 11 12 -40 -15 10 35 60 85 temperature (c) v refin (v) v fb (v) 0.50 0.65 0.80 0.95 1.10 1.25 0.50 0.65 0.80 0.95 1.10 1.25 i cdel( a) 1.8 1.9 2.0 2.1 2.2 -40 -15 10 35 60 85 temperature (c) en/ss vin vout phase en/ss vin vout phase
ISL8130 fn7954 rev.4.00 page 12 of 23 mar 24, 2017 figure 21. pgood pull-up delay at start up, buck converter figure 22. pgood pull-down at shutdown, buck converter figure 23. soft-start waveform, no pre-biased, boost converter figure 24. soft-start wave form, pre-biased, boost converter figure 25. overcurrent protection, buck converter figure 26. overcurrent protection, boost converter typical performance curves oscilloscope plots are taken using the ISL8130eva l1z evaluation board for buck converter or ISL8130eval2z for boost converter, v in = 12v, v out = 5v for buck converter or v out = 32v for boost converter unless otherwise noted. (continued) en/ss pgood vout cdel cdel = 0.1f en/ss pgood vout cdel cdel = 0.1f en/ss vin vout phase en/ss vin vout phase en/ss vout iinductor pgood en/ss vout iinductor vin
ISL8130 fn7954 rev.4.00 page 13 of 23 mar 24, 2017 figure 27. ocp entry and recovery, buck converter figure 28. ocp entry and recovery, boost converter figure 29. efficiency vs load current, buck converter, upper and lower mosfet: bsc057n03ls x 2; inductor: ser2010-901 figure 30. efficiency vs load current, boost converter, mosfet: bsc100n06ls; inductor: we 74477110 figure 31. load transient, buck converter, inductor: ser2010-901; c out : 2*16sepc180mx figure 32. load transient, boost converter, inductor: we 74477110; c out : 2*220f 50v, 42m esr typical performance curves oscilloscope plots are taken using the ISL8130eva l1z evaluation board for buck converter or ISL8130eval2z for boost converter, v in = 12v, v out = 5v for buck converter or v out = 32v for boost converter unless otherwise noted. (continued) en/ss vout iout pgood en/ss vout iinductor vin 0.80 0.85 0.90 0.95 1.00 0 5 10 15 20 25 f sw = 280khz v in = 12v, v out = 5v load current (a) efficiency 0 0.25 0.50 0.75 1.00 1.25 0.80 0.85 0.90 0.95 1.00 f sw = 320khz v in = 12v, v out = 32v v in = 6v, v out = 32v load current (a) efficiency istep: 0a to 25a 3a/s i out, 10a/div v out , ac, 500mv/div v in = 12v, v out = 5v istep: 0.5a to 1.25a 3a/s i out, 0.5a/div v out , ac, 50mv/div v in = 12v, v out = 32v
ISL8130 fn7954 rev.4.00 page 14 of 23 mar 24, 2017 functional description initialization the ISL8130 automatically initializes upon receipt of power. the power-on reset (por) function moni tors the internal bias voltage generated from ldo output (vcc5) and the enss pin. the por function initiates the soft-start operation after the vcc5 exceeds the por threshold. the por functi on inhibits operation with the chip disabled (enss pin <1v). the device can operate from an input supply voltage of 5.5v to 24v connected directly to the vin pin using the internal 5v linear regulator to bias the chip and supply the gate drivers. for 5v 10% applications, connect vin to vcc5 to bypass the linear regulator. refer to table 1 . shutdown when enss pin is below 1v, the regulator is disabled with the pwm output drivers tri-stated. wh en disabled, the ic power will be reduced. soft-start/enable the ISL8130 soft-start function uses an internal current source and an external capacitor to re duce stresses and surge current during start-up. when the output of the internal linear regulator reaches the por threshold, the por function initiates the soft-start sequence. an internal 10a current source charges an external capacitor on the enss pin linearly from 0v to 3.3v. when the enss pin voltage reaches 1v typically, the internal 0.6v reference begins to charge following the dv/dt of the enss voltage. as the soft-start pin charges from 1v to 1.6v, the reference voltage charges from 0v to 0.6v. figure 19 on page 11 shows a typical soft-start sequence. start-up into pre-biased load the ISL8130 is designed to power-up into a pre-biased load. during the soft starting, the error amplifier compares the voltage of the fb pin and the rising refe rence voltage given by the enss pin. the comp pin is held down if the vfb is greater than the rising reference voltage, thus inhibiting switching. the ISL8130 starts switching when the rising reference voltage exceeds the fb pin voltage. ISL8130 operates in ccm afterwards. the waveform for this condition is shown in figure 23 on page 12 . external reference/tracking if the refin pin is tied to vcc5, then the internal 0.6v reference is used as the error amplifier non-inverting input. if the refin is connected to an external voltage source between 0.6v to 1.25v, then this external voltage is used as the reference voltage at the positive input of the error amplifier. power-good the pgood pin can be used to mo nitor the status of the output voltage. pgood will be true (open-drain) when the fb pin is within 10% of the reference and the enss pin has completed the soft-start ramp. the cdel is used to set the pgood active delay after soft-start. after the enss pin completes its soft-start ramp, a 2a current begins charging the cdel capacitor to 2.5v. the capacitor will be quickly discharged before pgood goes high. the programmable delay can be used to sequence multiple converters or as a low-true reset signal. if the voltage on the fb pin exceeds 10% of the reference, the pgood will go low after 1s of noise filtering. overcurrent protection the overcurrent protection (ocp) function protects the converter from an overcurrent condition. the ocp circuit compares voltages at the ocset and the isen pin and signals an overcurrent condition when isen drops below ocset. voltage at the ocset pin acts as a reference and is established by a resistor connected to this pin from the input supply rail. an internal current source draws a current i ocset (typically 100a) from the ocset pin resulting in a voltage at the pin given by equation 1 . the isen pin is connected to a current sensing resistor that senses the current drawn from the input supply. this current sensing resistor could be the r ds(on) of the upper mosfet if the ISL8130 is used in a buck configuration. please refer to the ? block diagram ? on page 4 for more details. voltage at the isen pin is given by equation 2 . combining equations 1 and 2 gives the overcurrent trip point as given in equation 3 . when ugate is high, current throug h the sense resistor increases. if it increases enough to make v isen smaller than v ocset , an overcurrent event is registered for that clock cycle, a counter is incremented, and the ugate pulse is immediately terminated. if an overcurrent condition is registered for eight consecutive cycles, the ISL8130 enters into a soft-start hiccup mode. during hiccup, the external capacitor on the enss pin is discharged. after the capacitor is discharged, it is re leased and a soft-start cycle is initiated. there are three dummy so ft-start delay cycles to allow the power devices to cool down an d to alleviate the thermal stress in overload or short circuit conditions. at the fourth soft-start cycle, the output starts a normal soft-start cycle, and the output tries to ramp. table 1. input supply configuration input pin configuration 5.5v to 24v connect the input to the vin pin. the vcc5 pin will provide a 5v output from the internal ldo. connect pvcc to vcc5. 5v 10% connect the input to the vcc5 pin. connect the pvcc and vin pins to vcc5. v ocset v in r C ocset xi ocset = (eq. 1) v isen v in r C cs xi in = (eq. 2) i oc r ocset xi ocset r cs ------------------------------------------------- = (eq. 3)
ISL8130 fn7954 rev.4.00 page 15 of 23 mar 24, 2017 it is important to connect the oc set and isen traces right across the current sensing resistor for good accuracy of the ocp threshold. a kelvin connection is recommended to avoid noise coupling. in a buck configuration, the oc tr ip point varies mainly due to the upper mosfets r ds(on) variations. to avoid overcurrent tripping in the normal operating load range, find the r ocset resistor from equation 1 with: 1. the maximum r ds(on) at the highest junction temperature. 2. determine , where ? i is the output inductor ripple current. a small ceramic capacitor should be placed in parallel with r ocset to smooth the voltage across r ocset in the presence of switching noise on the input voltage. both the r ocset and the filtering cap should be placed close to the ISL8130. the ocp function is active once the enss reaches the enable threshold voltage. over-temperature protection the ISL8130 is protected against over-temperature conditions. when the junction temperature exceeds +150c, the pwm shuts off. normal operation is resumed when the junction temperature decreases to 130c. undervoltage if the voltage on the fb pin is less than 85% of the reference voltage for eight consecutive pwm cycles, then the circuit enters into soft-start hiccup mode. this mode is identical to the overcurrent hiccup mode. this undervoltage protection is disabled if the enss does not reach 3.3v. overvoltage protection if the voltage on the fb pin exceeds the reference voltage by 15%, the lower gate driver is turned on continuously to discharge the output voltage. if the overvoltage condition continues for 32 consecutive pwm cycles, then the ch ip is turned off with the gate drivers tri-stated. the voltage on the fb pin will fall and reach the 15% undervoltage threshold. after eight clock cycles, the chip will enter soft-start hiccup mode. this mode is identical to the overcurrent hiccup mode. this overvoltage protection is disabled if the enss does not reach 3.3v. gate control logic the gate control logic translates pwm control signals into the mosfet gate drive signals prov iding necessary amplification, level shifting and shoot-through pr otection. also, it has functions that help optimize the ic performance over a wide range of operational conditions. since mosfet switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower mosfets. the lower mosfet is not turned on until the gate-to-source voltage of the upper mosfet has decreased to less than approximately 1v. similarly, the upper mosfet is not turned on until the gate-to-source voltage of the lower mosfet has decreased to le ss than approximately 1v. this allows a wide variety of upper and lower mosfets to be used without a concern for simultaneous conduction or shoot-through. in a boost converter configuration, the lgate signal may be left floating. application guidelines layout considerations as in any high frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located as close together as possible using ground plane construction or single point grounding. figure 33 shows the critical power components of the buck converter. to minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. the components shown in figure 33 should be located as close together as possible. note that the capacitors, c in and c o , each represent numerous physical capacitors. locate the ISL8130 within three inches of the mosfets, q 1 and q 2 . the circuit traces for the mosfets? gate and source connections from the ISL8130 must be sized to handle up to 1a peak current. figure 34 on page 16 shows the circuit traces that require additional layout consideration. use single point and ground plane construction for the circui ts shown. minimize any leakage current paths on the ss pin and locate the capacitor, c ss , close to the ss pin because the internal current source is only 10a. provide local v cc decoupling between vcc and gnd pins. locate the capacitor, c boot , as close as practical to the boot and phase pins. i oc for i oc i out max ?? ? i ?? 2 ? + ? gnd l o c o lgate ugate phase q1 q2 d2 figure 33. printed circuit board power and ground planes or islands v in v out return ISL8130 c in load
ISL8130 fn7954 rev.4.00 page 16 of 23 mar 24, 2017 all control traces, such as feedback resistor divider connection and compensation network connect ion, should be placed away from the high dv/dt node. use kelvin sensing connection for current sensing. general powerpad design considerations figure 35 is an example of how to us e vias to remove heat from the ic. we recommend you fill the therma l pad area with vias. a typical via array would be to fill the thermal pad footprint with space, such that the vias are center on center three times the radius apart from each other. keep the vias small, but not so small that their inside diameter prevents solder wicking through the holes during reflow. connect all vias to the ground plane. the vias should have a low thermal resistance for efficient he at transfer. it is important to have a complete connection of the plated through-hole to each plane. feedback compensation figure 36 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage (v out ) is regulated to the reference voltage level. the error amplifier (error amp) output (v e/a ) is compared with the oscillator (osc) triangular wave to provide a pulse-width modulated (pwm) wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l o and c o ). the modulator transfer function is the small-signal transfer function of v out /v e/a . this function is dominated by a dc gain and the output filter (l o and c o ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (v in ) divided by the peak-to- peak oscillator voltage ? v osc . modulator break frequency equations the compensation network consists of the error amplifier (internal to the ISL8130) and the impedance networks, z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with th e highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180. equations 6 through 9 relate to the compensation network?s poles, zeros, and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) in figure 36 . use the following guidelines for locating the poles and zeros of the compensation network. figure 34. printed circuit bo ard small signal layout guidelines +5v ISL8130 enss gnd v cc boot d 1 l o c o v out load q 1 q 2 phase +vin c boot c vcc c ss figure 35. pcb via pattern figure 36. voltage - mode buck converter compensation design v out osc reference l o c o esr vin dv osc error amp pwm driver (parasitic) - ref r 1 r 3 r 2 c 3 c 2 c 1 comp v out fb z fb ISL8130 z in comparator driver detailed compensation components phase v e/a + - + - z in z fb + v out v ref x 1 r 1 r 4 ------- + ?? ?? ?? = r 4 f lc 1 2 ? l o c o ? ? -------------------------------------- - = (eq. 4) f esr 1 2 ? esr c o ? ?? ? -------------------------------------------- - = (eq. 5)
ISL8130 fn7954 rev.4.00 page 17 of 23 mar 24, 2017 compensation break frequency equations 1. pick gain (r2/r1) for desired converter bandwidth 2. place 1st zero below filt er?s double pole (~75% f lc ) 3. place 2nd zero at filter?s double pole 4. place 1st pole at the esr zero 5. place 2nd pole at half the switching frequency 6. check gain against error amplifier?s open-loop gain 7. estimate phase margin - repeat if necessary figure 37 shows an asymptotic plot of the dc/dc converter?s gain vs frequency. the actual modulato r gain has a high gain peak due to the high q factor of the output filter and is not shown in figure 37 . using the previously mentione d guidelines should give a compensation gain similar to th e curve plotted. the open loop error amplifier gain bounds th e compensation gain. check the compensation gain at f p2 with the capabilities of the error amplifier. the loop gain is cons tructed on the log-log graph of figure 37 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function to th e compensation transfer function and plotting the gain. the compensation gain uses external impedance networks z fb and z in to provide a stable, high ba ndwidth (bw) overall loop. a stable control loop has a gain cr ossing with -20db/decade slope and a phase margin greater than 45. include worst case component variations when determining phase margin. component selection guidelines buck converter component mosfet considerations the logic level mosfets are chosen for optimum efficiency given the potentially wide input voltage range and output power requirements, two n-channel mosfets for the buck converter. these mosfets should be selected based upon r ds(on) , gate supply requirements, and thermal management considerations. the power dissipation includes two loss components: conduction loss and switching loss. these lo sses are distributed between the upper and lower mosfets according to duty cycle (see equations 10 and 11 ). the conduction losses are the main component of power dissipation for the lower mosfets. only the upper mosfet has significant switching losses since the lower device turns on and off into near zero voltage. the equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower mosfet?s body diode. a large gate-charge increases the switching time, t sw , which increases the upper mo sfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal- resistance specifications. output inductor selection the pwm converters require output inductors. the output inductor is selected to meet the output voltage ripple requirements. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current and output capacitor(s) esr. the ripple voltage expression is given in the capa citor selection section and the ripple current is approximated by equation 12 : output capacitor selection the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. selection of output ca pacitors is also dependent on the output inductor, thus some inductor analysis is required to select the output capacitors. one of the parameters limiting the converter?s response to a load transient is the time required for the inductor current to slew to its new level. the response time is the time interval required to slew the inductor current from an initial current value to the load current level. during this interval, the difference between the inductor current and the transien t current level must be supplied by the output capacitor(s). mini mizing the response time can minimize the output capacitanc e required. also, if the load f z1 1 2 ? r ? 2c1 ? ---------------------------------- = (eq. 6) f p1 1 2 ? r2 ? c1 c2 ? c1 c2 + ---------------------- ?? ?? ? ------------------------------------------------------ - = (eq. 7) f z2 1 2 ? r1 r3 + ?? c3 ? ? ----------------------------------------------------- - = (eq. 8) f p2 = 1 2 ? r3 c3 ? ? ---------------------------------- (eq. 9) 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 f lc f esr compensation gain (db) frequency (hz) gain 20log (vin/dv osc ) modulator gain 20log (r 2 /r 1 ) loop gain figure 37. asymptotic bode plot of converter gain p upper i o 2 ?? r ds on ?? ?? v out ?? v in --------------------------------------------------------------- i o ?? v in ?? t sw ?? f sw ?? 2 --------------------------------------------------------- - + = (eq. 10) p lower i o 2 ?? r ds on ?? ?? v in v out C ?? v in --------------------------------------------------------------- --------------- - = (eq. 11) ? i l v in v out C ?? v out ?? f s ?? l ?? v in ?? --------------------------------------------------------- - = (eq. 12)
ISL8130 fn7954 rev.4.00 page 18 of 23 mar 24, 2017 transient rise time is slower than the inductor response time, as in a hard drive or cd drive, it reduces the requirement on the output capacitor. the maximum capacitor value required to provide the full, rising step, transient load current duri ng the response time of the inductor is shown in equation 13 : where c out is the output capacitor(s) required, l o is the output inductor, i tran is the transient load current step, v in is the input voltage, v o is output voltage, and dv out is the drop-in output voltage allowed during the load transient. high frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the equivalent series resistance (esr) and voltage rating requirements as well as actu al capacitance requirements. the output voltage ripple is due to the inductor ripple current and the esr of the output capacitors as defined by equation 14 : where i l is calculated in the ? output inductor selection ? on page 17 . high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load circuitry for specific decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applications fo r the bulk capacitors. in most cases, multiple, small-case electrolytic capacitors perform better than a single large-case capacitor. input capacitor selection the important parameters for the bulk input capacitor(s) are the voltage rating and the rms current rating. for reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a conservative guideline. the ac rms input current varies with the load. the total rms current supplied by the input capacitance is given by equation 15 : where dc is duty cycle of the buck converter. use a mix of input bypass capacitors to control the voltage ripple across the mosfets. use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capacitors can be placed very close to the upper mosfet to suppress the voltage induced in the parasitic circuit impedances. boost converter layout considerations figure 38 shows the critical power components of the boost converter. to minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. the components shown in figure 38 should be located as close together as possible. boost converter component selection mosfet considerations the boost converter mosfet has both conduction loss and switching losses ( equation 16 ). the conduction loss p cond is given by equation 17 : where i rmsfet is the mosfet rms drain current ( equation 18 ). dc is duty cycle of the boost converter. the switching loss is shown by equation 19 : t swon and t swoff are the mosfet turn on and turn off time respectively and vm is the plateau voltage during the mosfet turn-on and turn-off ( equations 20 and 21 ): c out l o ?? i tran ?? 2 2v in v o C ?? dv out ?? ---------------------------------------------------------- - = (eq. 13) v ripple ? i l esr ?? = (eq. 14) i rmsx dc dc 2 C i o ? = (eq. 15) phase l bst c o ugate q1 d2 figure 38. printed circuit board power and ground planes or islands vin v out return ISL8130 c in load r cs p fet p cond i out ?? v out ?? 2 t swon t swoff + ?? f sw ?? 2v in ? --------------------------------------------------------------- ------------------------------------------------- + = (eq. 16) p cond i rmsfet 2 ?? r ds on ?? ? = (eq. 17) i rmsfet i out v out ? v in ----------------------------------- dc 1 ? i pp 2 12 --------------- - + ?? ?? ?? ? ? = (eq. 18) p sw i out ?? v out ?? 2 t swon t swoff + ?? f sw ?? 2v in ? --------------------------------------------------------------- ------------------------------------------------- = (eq. 19) t swon q gd 2 ? r gfet + ?? ? pvcc v m C ?? ------------------------------------------------------- - = (eq. 20) t swoff q gd 2 ? r gfet + ?? ? v m ------------------------------------------------------- - = (eq. 21)
ISL8130 fn7954 rev.4.00 page 19 of 23 mar 24, 2017 the optimum mosfet is usually that the conduction loss equals the switching loss. the worst ca se for the mosfet is at the minimum vin, when the inductor average current is the maximum. the equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the schottky diode. inductor selection for a boost converter, the output ripple is not a strong function of the boost inductor. the inductor is selected to meet the efficiency, size and thermal requirement. usually a smaller inductor is preferred for cost, size, and easy compensation. when a small inductor is used, the inductor ripple current is large incurring larger core loss. the ripple ration is usually from 30% to 50% ( equation 22 ): where is ? i r the desired ripple ratio. dc is the boost converter duty cycle. the dc inductor current is the maximum at the minimum v in ( equation 23 ). the maximum peak inductor current occurs at the minimum input ( equation 24 ). select the inductor using equation 22 . with saturation current higher than that calculated with equation 24 . make sure the inductor can handle the thermal stress. output capacitors selection the important parameters for the bulk output capacitor(s) are the voltage rating, the rms current rating and output ripple. for reliable operation, select bulk capacitors with voltage and current ratings above the maximum output voltage, which should be the ovp threshold and largest rms current required by the circuit. the capacitor voltage rati ng should be at least 1.25 times greater than the maximum output voltage and 1.5 times is a conservative guideline. the ac rms output current varies with the load and v in . the total rms current filtered by the output capacitance is given by equation 25 : the worst case is at full load and minimum v in . when the maximum ac ripple current is as shown in equation 26 : use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capacitors can be placed very close to the mosfet and diode to suppress the voltage induced in th e parasitic circuit impedances. current sensing resistor selection a small current sensing resistor is preferred for high efficiency conversion. an r cs that is too small might not render an accurate overcurrent protection threshold. the current sensing resistor shou ld be selected so that the voltage across the current sensing resistor at ocp is greater than 500mv for accurate ocp trip threshold ( equation 27 ): where i pkind is the maximum inductor peak current. it is recommended to have a 25% margin for load transient and variation. then the resistor sh ould be sized to survive the maximum stress at ocp ( equation 28 ). input capacitor selection the input current ripple for a boost converter is much smaller than the output ripple. the input capacitor of the boost converter is to filter out the inductor ripple current and to stabilize the power supply and the boost converter. the input capacitor should take the input rms current ( equation 29 ). if the boost converter is powered by another dc/dc converter with sufficient output capacitors, a small ceramic capacitor can be used for the input capacitor. boost converter compensation modulator break frequency equations the modulator dc gain is ( equation 30 ): v osc is the internal oscillator output amplitude, which is 1.25v, dc is the boost converter duty cycle. the boost converter double pole is a function of the duty cycle, inductor and output capacitor ( equation 31 ). the output capacitor, esr, adds a zero to the loop gain ( equation 32 ). the right-half-plane zero is a fu nction of load current, vin, and the boost inductance. the rh p zero causes phase lag, decreasing phase margin. it is recommended to have the closed loop gain cross 0db at 1/3 of the f rhp ( equation 33 ). l bst v out f sw ? i r i out ---------------------------------- - dc 1 dc C ?? 2 = (eq. 22) i rmsind i out v out ? v in ----------------------------------- 1 ? i pp 2 12 --------------- - + ? = (eq. 23) i pkind i rmsind 1 2 -- - v inmin l bst f sw ------------------------- 1 v inmin v out -------------------- C ?? ?? ?? + = (eq. 24) i rmsout i out v out v in --------------- - 1 C ? = (eq. 25) i rmsout i outmax v out v inmin -------------------- 1 C ? = (eq. 26) r cs 500mv i pkind 1m in arg + ?? ? ----------------------------------------------------------- - = (eq. 27) p rcs r cs i pkind 1m in arg + ?? ? ?? 2 = (eq. 28) i rmsin 1 12 ------ v out l bst f sw ? ----------------------------- dc 1 dc C ?? ? ?? ?? ?? ? = (eq. 29) g dc v out v osc 1dc C ?? ? --------------------------------------------- = (eq. 30) f lc 1dc C 2 ? l bst c o ? ?? ? ---------------------------------------------- = (eq. 31) f esr 1 2 ? esr c o ? ?? ? -------------------------------------------- - = (eq. 32) f rhp v in 1dc C ?? ? 2 ? i out l bst ? ?? ? --------------------------------------------------- = (eq. 33)
ISL8130 fn7954 rev.4.00 page 20 of 23 mar 24, 2017 compensation break frequency equations the compensation network consists of the error amplifier (internal to the ISL8130) an d the impedance networks, z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180. the following equations relate to the compensation network?s poles, zeros, and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) in figure 36 on page 16 . use the following guidelines for locating the poles and zeros of the compensation network. figure 39 shows an asymptotic plot of the boost converter?s gain vs frequency. using the previous ly mentioned guidelines should give a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 with the capabilities of the error amplifier. the loop gain is cons tructed on the log-log graph of figure 39 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function to th e compensation transfer function and plotting the gain. 1. pick gain (r 2 /r 1 ) for desired converter bandwidth 2. place 1st zero below filt er?s double pole (~75% f lc ) 3. place 2nd zero at filter?s double pole 4. place 1st pole at the right half plane zero, f rhp 5. place 2nd pole at half the switching frequency 6. check gain against error amplifier?s open-loop gain 7. estimate phase margin - repeat if necessary in applications where the rhp zero makes the stabilizing the converter very difficult, it is recommended to increase the output capacitor. f z1 1 2 ? r ? 2c1 ? ---------------------------------- = (eq. 34) f p1 1 2 ? r2 ? c1 c2 ? c1 c2 + ---------------------- ?? ?? ? ------------------------------------------------------ - = (eq. 35) f z2 1 2 ? r1 r3 + ?? c3 ? ? ----------------------------------------------------- - = (eq. 36) f p2 = 1 2 ? r3 c3 ? ? ---------------------------------- (eq. 37) 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 f lc f esr compensation gain (db) frequency (hz) gain 20log (vo/(dv osc *(1-d))) modulator gain 20log (r 2 /r 1 ) loop gain figure 39. asymptotic bode plot of converter gain f rhp
fn7954 rev.4.00 page 21 of 23 mar 24, 2017 ISL8130 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2012-2017. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. for the most updated datasheet, application notes, related docume ntation, and related parts, see the respective product informa tion page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for in formational purposes only and is believ ed to be accurate, but not warranted. please visit our website to make sure you have the latest revision. date revision change mar 24, 2017 fn7954.4 updated 8th bullet under features on page 1. added the i/o column to the ?pin descriptions? on page 2. updated figure 3 on page 4. changed from ?v refout ? to ?v revin ? in the test conditions for parameter ?buffered output voltage - external reference?. updated note 1 on page 2. replaced products section with about intersil section. updated pod l20.4x4 with the latest revision changes are as follows: -added +/- 0.05 tolerances to dimensions in top view and bottom view. sep 26, 2012 fn7954.3 ?overcurrent protection? on page 14 - changed vocset to iocset equation 22 on page 19 -- added iout to the equation. ?output capacitors selection? on page 19 - changed ?input ? to ?output? - deletetd ?use a mix of input capacitors to control the voltage ripple across mosfets.? feb 22, 2012 fn7954.2 correction to ?typical step down dc/dc appl ication schematic? on page 5. co nnections corrected for vin and pvcc. removed capacitor c14 and gnd from refout. feb 13, 2012 fn7954.1 made correction to units for shutdown and operating currents on page 7 from a to ma. ?pwm controller gate drivers? on page 8 - changed ty pical value in pull-down resistance from 2.6 to 2.0 and changed typical value in pull-up resistance from 2.0 to 2.6 load transient figures 31 and 32 on page 13 replaced to show a clearer description of the waveforms. feb 9, 2012 fn7954.0 initial release
ISL8130 fn7954 rev.4.00 page 22 of 23 mar 24, 2017 package outline drawing m20.15 20 lead quarter size outl ine plastic package (qsop) rev 2, 1/11 detail "x" side view typical recommended land pattern top view 0.010 (0.25) 0.007 (0.18) 8 0.050 (1.27) 0.016 (0.41) 20 123 index area (0.635 bsc) 0.025 1 2 0.025 (0.64) x 18 0.220(5.59) seating plane 0.015 (0.38) x 20 0.060 (1.52) x 20 3 20 3 4 5 0.244 (6.19) 0.228 (5.80) 0.157 (3.98) 0.150 (3.81) 0.344 (8.74) 0.337 (8.56) 0.069 (1.75) 0.053 (1.35) 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0 0.0196 (0.49) 0.0099 (0.26) 0.061 max (1.54 mil) notes: 1. symbols are defined in the mo series symbol list in secti on 2.2 of publication number 95. 2. dimensioning and tolerancing conform to amse y14.5m-1994. 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.1 5mm (0.006 inch) per side. 4. dimension does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. length of terminal for soldering to a substrate. 7. terminal numbers are s hown for reference only. 8. dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in ex cess of dimension at maximum material condition. 9. controlling dimens ion: inches. converted millimete r dimensio ns are not necessarily exact. 6 0.25 0.010 gauge plane 8 for the most recent package outline drawing, see m20.15
ISL8130 fn7954 rev.4.00 page 23 of 23 mar 24, 2017 package outline drawing l20.4x4 20 lead quad flat no-lead plastic package rev 4, 6/15 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance: decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view bottom view side view a b 6 pin 1 index area (4x) 0.15 4x 0.50 0.05 2.0 0.05 16x 20 16 15 11 pin #1 index area 6 2.10 0.15 5 1 0.25 +0.05/-0.07 0.10 m ab c 20x 0.6 +0.15/-0.25 4 6 10 base plane seating plane 0.10 see detail "x" 0.08 c c c 0.90 0.1 0.2 ref c 0.05 max. 0.00 min. 5 (3.6 typ) ( 2.10) (20x 0.8) (20x 0.5) (20x 0.25) 4.00 0.05 4.00 0.05 for the most recent package outline drawing, see l20.4x4

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